The present invention relates to a semiconductor memory device including a semiconductor integrated circuit controlled by serial input signal pulses.
A conventional semiconductor integrated circuit carries out predetermined actions by decoding serial input signal pulses sent from a CPU 20 and so on as shown in FIG. 2. An outline of actions thereof will be explained hereinafter referring to the drawings. For more specific and clear explanation, here is illustrated with a semiconductor non-volatile memory device comprising electrically rewritable non-volatile memory elements. (It is hereinafter referred to as EEPROM.)
Serial input signal pulses from CPU 20 and so on separate according to their function and are sent respectively into a CS (Chip Select) input terminal 1, an SK (Serial Clock) input terminal 2, and a DI (Data In) input terminal 3. Then they go through an input signal control circuit 4, and are sent sequentially to a shift register 5 for instruction, a shift register 6 for address, and a shift resister 7 for data. The contents sent to the shift register 5 for instruction and the shift register 6 for address are decoded by an instruction decoder 8 and then sent an instruction order to an instruction control circuit 9. Furthermore, the instruction control circuit 9 controls the data flow of the serial input signal pulses outputted from the input signal control circuit 4.
In general, EEPROM memory cells 21 controlled by the serial input signal pulses have a function of writing an arbitrary data to the specified address and reading same. It sometimes includes the additional function such as allowing the writing operation and prohibiting same.
Adding to data writing operation, a semiconductor memory device using electrically rewritable non-volatile memory cells generally requires longer time in writing than in reading. In other words, it needs several tens of microseconds to a few milliseconds. Thus, some functions of EEPROM can respond promptly to signals given by CPU and so on, the others cannot.
READ (reading) order and PEN (permitting to write) order are typical examples of the order group classified as a prompt response function. On the other hand, PROGRAM (writing) order is one of the orders which the device cannot respond to promptly and have to wait till the end thereof.
However, in a conventional EEPROM comprising a serial input signal circuit shown in FIG. 2, when the processing speed is slower than the speed of serial signal pulses given by CPU and so on, as seen in the writing operation, it needs to wait for that processing to finish. Thus, it restricts considerably the processing ability of the device employing EEPROM per unit time.
Then, another conventional EEPROM comprising a serial signal inputting circuit, which was directed to solve the foregoing problem, will be explained referring to FIG. 3. Similarly to FIG. 2, serial signal pulses from CPU and so on are functionally divided into the CS input terminal 1, the SK input terminal 2, and the DI input terminal 3. Then, they go through the input signal controlling circuit 4 and are sent sequentially to the shift register 5 for instruction, the shift register 6 for address, and the shift register 7 for data. What the shift register 5 for instruction and the shift register 6 for address receive is decoded by the instruction decoder 8, then is sent an instruction order to the instruction control circuit 9 and controls the data flow of the serial input signal pulses outputted from the input signal control circuit 4.
In addition, the contents of the shift register 6 for address is stored in an address latch 11 and is retained therein. On the other hand, the contents of the shift register 7 for data are stored in a data latch 12 and are retained therein.
Thus, all the information needed for writing operation is retained in the instruction control circuit 9, the address latch 11 and the data latch 12. So, even in the execution of writing operation, serial signal pulses from CPU and so on are given to the CS input terminal 1, the SK input terminal 2, and the DI input terminal 3, and after going through the input signal control circuit 4 they are sequentially sent to the shift register 5 for instruction, the shift register 6 for address, and the shift register 7 for data. At that time, the subjects sent to the shift register 5 for instruction and the shift register 6 for address are decoded by the instruction decoder 8 and are sent an instruction order to the instruction control circuit 9. Therefore, even in the execution of writing operation, appropriate performance in accordance with serial signal pulses received from CPU and so on can be realized.
However, in a conventional construction of a serial signal inputting circuit, in the execution of writing operation, address and data both of which are once stored in a shift register have to be transferred for their retainment to the address latch 11 and the data latch 12 respectively. Thus, not only an address latch and a data latch but also a control circuit for forwarding data are provided, the circuit scale of EEPROM has to be very large as a result.
Then, the present invention is directed to solve the above problem of conventional semiconductor memory devices and the purpose thereof is to obtain a semiconductor integrated circuit being able to receive another order during the execution of an order requiring lone time to do, without providing a large-scale circuit.
In other words, the present invention is directed to enable to receive another order during the execution of an order which requires much time to do. Actually, the purpose is that it is possible that CPU can ask whether writing operation has finished or not and EEPROM can respond in accordance therewith. As stated before, a semiconductor nonvolatile memory device comprising electrically rewritable non-volatile memory cells takes generally several tens of microseconds to a few milliseconds to write, which is much longer than the speed of serial pulses from CPU outputs. Then, after EEPROM starts writing operation, CPU sets out another action and ask EEPROM whether it is in the excution of writing operation or not so as to know the end of the writing operation. This is for raising the ability of the semiconductor memory device to its maximum performance.